1. Field of the Invention
The present invention relates to a bandgap reference circuit and bandgap reference current source, and more particularly, to a bandgap reference circuit and bandgap reference current source with reduced layout area.
2. Description of the Prior Art
A stable reference voltage source or current source immune to temperature variation, e.g. a bandgap reference circuit, is usually applied in analog circuits to provide a reference voltage or reference current, for maintaining accurate operations of a power source or other circuits. In short, a bandgap reference current source sums a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current at a proper ratio, such that a PTAT component and a CTAT component are cancelled, generating a zero temperature correlated (zero-TC) current.
In detail, please refer to FIG. 1, which is a schematic diagram of a bandgap reference current source 10 in the prior art. The bandgap reference current source 10 includes a start-up circuit 100 and a bandgap reference circuit 102. The start-up circuit 100 activates operations of the bandgap reference circuit 102 when a system voltage VDD is greater than source-to-gate voltages of P-type metal oxide semiconductor (MOS) transistors 104, 106, i.e. VDD>2 VSG. As shown in FIG. 1, since input voltages VA, VB of positive and negative input terminals of an operational amplifier (OP) 108 are identical in the bandgap reference circuit 102, i.e. VA=VB=VEB1, a PTAT current Iptat can be generated from base-to-emitter voltages VEB1, VEB2 of BJTs Q1, Q2 and a resistor Rptat with a resistance R as shown in Eq. 1:
                              Iptat          =                                                                      V                  ⁢                                                                          ⁢                  E                  ⁢                                                                          ⁢                  B                  ⁢                                                                          ⁢                  1                                -                                  V                  ⁢                                                                          ⁢                  E                  ⁢                                                                          ⁢                  B                  ⁢                                                                          ⁢                  2                                            R                        =                                                            V                  T                                ⁢                ln                ⁢                                                                  ⁢                K                            R                                      ,                            (                  Eq          .                                          ⁢          1                )            
where K denotes that the BJT Q2 can be taken as K BJTs Q1 connected in parallel. Since a threshold voltage VT is PTAT, by referring to Eq. 1, the PTAT current Iptat carried by the resistor Rptat is also PTAT.
On the other hand, a CTAT current Ictat can be generated from the base-to-emitter voltage VEB1 of the BJT Q1 and a resistor Rctat with a resistance L*R as shown in Eq. 2:
                                          I            CTAT                    =                                    VEB              ⁢                                                          ⁢              1                                      L              *              R                                      ,                            (                  Eq          .                                          ⁢          2                )            
where the CTAT current Ictat carried by the resistor Rctat is CTAT, since the base-to-emitter voltage VEB1 is CTAT. As a result, if the resistance L*R of the resistor Rctat is properly adjusted, a zero-TC current Iref can be generated by summing the PTAT current Iptat and the CTAT current Ictat as shown in Eq. 3:
                              Iref          =                                    Iptat              +              Ictat                        =                                                                                V                    T                                    ⁢                  ln                  ⁢                                                                          ⁢                  K                                R                            +                                                V                  ⁢                                                                          ⁢                  E                  ⁢                                                                          ⁢                  B                  ⁢                                                                          ⁢                  1                                                  L                  *                  R                                                                    ⁢                                  ⁢                                            ∂              Iref                                      ∂              T                                =                                                                                          ln                    ⁢                                                                                  ⁢                    K                                    R                                *                                                      ∂                                          V                      T                                                                            ∂                    T                                                              +                                                1                                      L                    *                    R                                                  *                                                                            ∂                      V                                        ⁢                                                                                  ⁢                    E                    ⁢                                                                                  ⁢                    B                    ⁢                                                                                  ⁢                    1                                                        ∂                    T                                                                        =            0                          ,                                  ⁢                              ⇒            L                    =                                    -                                                                                          ∂                      V                                        ⁢                                                                                  ⁢                    E                    ⁢                                                                                  ⁢                    B                    ⁢                                                                                  ⁢                    1                                                        ∂                    T                                                                                                              ∂                                              V                        T                                                                                    ∂                      T                                                        ⁢                  ln                  ⁢                                                                          ⁢                  K                                                      ≈                          -                                                -                  1.6                                                  0.085                  ⁢                  ln                  ⁢                                                                          ⁢                  K                                                                                        (                  Eq          .                                          ⁢          3                )            
where a component of the base-to-emitter voltage VEB1 and a component of the threshold voltage VT after partial differential operations of time are −1.6 mv/C and 0.085 mv/C, respectively. Therefore, as can be seen from Eq. 3, when L=1.6/0.085 lnK, the zero-TC current Iref is zero-TC, and the zero-TC current Iref can be mirrored for output by current mirrors M1, M2, M3.
Please refer to FIG. 2A and FIG. 2B, which are schematic diagrams of the OP 108 shown in FIG. 1 optionally including an input pair of PMOS or NMOS transistors, respectively. When the OP 108 includes an input pair of PMOS transistors, the input voltages VA, VB of the input pair of the PMOS transistors Q3, Q4 are required to be less than VDD−VDS5−VSG3, and when the OP 108 includes an input pair of NMOS transistors, the input voltages VA, VB of the input pair of the NMOS transistors Q6, Q7 are required to be greater than VDS8+VGS7. Therefore, the input voltages VA, VB of the OP 108 including an input pair of PMOS transistors can be lower than those of the OP 108 including an input pair of NMOS transistors, such that power consumption of the BJTs Q1, Q2 shown in FIG. 1 can be reduced.
However, as shown in FIG. 1 and FIG. 2A, if the OP 108 includes an input pair of PMOS transistors, since the output voltage Vo equals the system voltage VDD minus a source-to-gate voltage VSGM1 of the current mirror M1, the input pair of the PMOS transistors will operate in linear region when the system voltage VDD rises, such that the OP 108 will not operate as expected. As a result, the OP 108 including an input pair of PMOS transistors can not be applied for a wider range of the system voltage VDD. In comparison, although the OP 108 including an input pair of NMOS transistors can be applied for a wider range of the system voltage VDD, the input voltages VA, VB can not be reduced, such that power consumption of the BJTs Q1, Q2 is increased.
Besides, in the bandgap reference current source 10, since the start-up circuit 100 starts operating when VDD>2 VGS, the start-up circuit 100 may not operate well due to process or temperature variation. In addition, the bandgap reference circuit 102 further needs to utilize a resistor with a resistance L*R to balance the CTAT current, wasting layout area. Thus, there is a need for improvement of the prior art.